#Kaspersky embedded alliance partners 64 Bit
The device has dual 64 bit (72b with ECC) DDR2 memory controllers to match the bandwidth requirements of the two cores. For applications that do share data between cores, low latency data sharing features are also present. With each core having its own L2 cache, it can be particularly efficient when the two cores are running separate operating systems and data sharing is limited. With a large backside L2 cache for each core, the e600 benefits from high bandwidth and low latency between the processor and the L2 cache. The e600 has an on-board 128-bit vector processor for efficient data movement (useful for copying TCP payloads from kernel space to user space) and for math functions that rival a DSP. These processors support up to 8 out-of-order instructions on the system bus that allows for making forward progress even while waiting for previous instructions to finish (ie, access to main memory required). Unpredictable branching is typical of code paths driven by largely random arrival of different types of packets. It avoids the extensive delays associated with flushing a long pipeline on mispredicted branches. This three-issue machine has a compact 7-stage pipeline which is particularly efficient with code that branches unpredictably.
The MPC8641D uses two high-performance superscalar e600 cores running at up to 1.5 GHz. MPC8641 device is "Not recommended for new designs", please use the replacement families Power Architecture ( T208x),
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